1. Field of the Invention
The invention relates generally to a technique for protection against electrostatic discharge damage of integrated circuits. More particularly, the invention relates to an electrostatic discharge protection circuit triggered by capacitive-coupling.
2. Description of the Related Art
Electrostatic discharge, hereinafter xe2x80x9cESD,xe2x80x9d is a common phenomenon the occurs during handling of semiconductor integrated circuit (xe2x80x9cICxe2x80x9d) devices. An electrostatic charge may accumulate for various reasons and produce potentially destructive effects on an IC device. Damage typically cm occur during a testing phase of IC fabrication or during assembly of the IC onto a circuit board, as well as during use of equipment into which the IC has bean installed. Damage to a single IC due to poor ESD protection in an electronic device can partially or sometimes completely hamper its functionality. EDS protection for semiconductor ICs is, therefore, a reliability issue.
ESD stress models are based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacture or handling. Three standard models, known as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) have been developed. The human-body model is set forth in U.S. Military Standard MIL-SID-883, Method 3015.6. This Military Standard models the electrostatic stress produced on an IC device when a human carrying an electrostatic charge touches the lead pins of the IC device. The machine model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying an electrostatic charge contacts the lead pins of the IC device. The charged device model describes the ESD current pulse generated when an IC device already carrying an electrostatic charge is grounded while being handled.
Referring to FIGS. 1 and 2, circuit diagrams of ESD protection circuits conventionally used respectively with an input pad and an output pad of an IC package are schematically depicted. As shown in FIG. 1, an NMOS transistor M1 is utilized protect an internal circuit 6 from the ESD stress that may appear at the input pad 5. The gate, source and bulk of the NMOS transistor M1 are all tied to circuit ground VSS. The drain of the NMOS transistor M1 is connected to the input pad 5. As shown in FIG. 2, an output buffer consisting of an NMOS transistor M2 and a PMOS transistor M3 is employed to protect the internal circuit 6 from ESD damage at the output pad 7. Accordingly, the gates of the NMOS and PMOS transistors are both coupled to the internal circuit 6, and the drains of the transistor, are tied together and to the output pad 7. Moreover, the source and bulk of the NMOS transistor M2 are tied together and to circuit ground VSS. The source and bulk of the PMOS transistor M3 are tied together and to a VDD power rail
However, in light of the trend toward submicron scale IC fabrication, MOS transistor vulnerability to ESD stress has been greatly reduced due to advanced bases, such as using lightly-doped drain (LDD) structures and clad silicide diffusions. In addition, the conventional ESD protection circuit design layout has a multi-finger structure. Therefore, during an ESD event, minority carriers will crowd within a local area and flow along the same direction and trigger meridian, finger to turn on, consequently resulting in local beating and degradation of the performance of EST) circuits configurated with finger-type NMOS
It is therefore an object of the invention to provide an electrostatic discharge protection circuit triggered by capacitive-coupling which can be used at an input pad or an output pad to protect the internal circuit from ESD damage.
It is another object of the invention to provide an electrostatic protecting circuit triggered by capacitive-coupling, having a capacitor including a metal pad and a polysilicon layer therebelow and having an increased coupling into without consuming extra layout area.
The invention achieves the above-identified objects by providing an electrostatic discharge protection circuit for protecting an internal circuit which includes a semiconductor substrate and a P-well region formed in the substrate. At least one contact region is formed in the P-well region, as is an isolating structure. A conducting layer is formed on the isolating structure and is coupled to the contact region. A dielectric layer is formed overlying the conducting layer, and a metal pad is formed on the dielectric layer, such that the metal pad, the dielectric layer, and the conducting layer form a capacitor for coupling ESD voltage to the P-well region when an ESD voltage appears at the pad.
Further, a first N-type heavily-doped region is formed in the P-well region and is coupled to the pad. A second N-type heavily-doped region for coupling to a circuit ground of the internal circuit is formed in the P-well, spaced apart and electrically isolated from the first N-type heavily-doped region. A gate structure is formed on the P-well region, between the first N-type heavily-doped region and the second N-type heavily-doped region, for connection to the circuit ground, such that the first N-type heavily-doped region, the second N-type heavily-doped region, the gate structure, and the P-well region form an NMOS transistor which bypasses ESD stress when an ESD voltage is coupled to the P-well region through the capacitor. The NMOS transistor is coupled to the circuit ground by a load connected between the contact region and the circuit ground, when the gate structure and the second N-type heavily-doped region are connected to the circuit ground. The load may be either a resistor or a second NMOS transistor.
Moreover, the invention achieves the above-identified objects by providing an electrostatic discharge protection circuit coupled to a power rail. The circuit includes a semiconductor substrate and an N-well region formed on the substrate. At least one contact region is formed in the N-well region. An isolating structure is formed on the substrate, and a conducting layer is formed on the isolating structure and is coupled tothe contact region. A dielectric layer is formed overlying the conducting layer, and a metal pad is formed on the dielectric layer, such that the metal pad, the dielectric layer, and the conducting layer form a capacitor for coupling ESD stress to the N-well region when an ESD voltage appears at the pad.
A first P-type heavily-doped region is formed in the N-well region and is coupled to the pad. A second P-type heavily-doped region is formed in the N-well, spaced apart and electrically isolated from the first P-type heavily-doped region, for coupling to the power rail. A gate structure is formed on the N-well region between the first P-type heavily-doped region and the second P-type heavily-doped region, for connection to the power rail, such that the first P-type heavily-doped region, the second P-type heavily-doped region, the gate structure and the N-well region form a PMOS transistor which bypasses ESD stress when an ESD voltage is coupled to the one N-well region through the capacitor.
The PMOS transistor is coupled to the power end by a load connected between the contact region and the power rail, when the gate structure is connected to the power rail. The load may be either a resistor or mother PMOS transistor.